Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm

The current semiconductor technology allows integration of all components onto a single chip called system-on-chip (SoC), which scales down the size of product and improves the performance. When a system becomes more complicated, testing process, such as test scheduling, becomes more challenging. Recently, peak power has also been considered as constraints in the test scheduling problem. Besides these constraints, some add-on techniques including pre-emption and non-consecutive test bus assignment have been introduced. The main contribution of each technique is the reduction of idling time in the test scheduling and thus reducing the total test time. This paper proposes a power-aware test scheduling called enhanced rectangle packing (ERP). In this technique, we formulate the test scheduling problem as the rectangle packing with horizontally and vertically split-able items (rectangles) which are smaller to fill up more compactly the test scheduling floor plan. Experimental results conducted on ITC'02 SoC benchmark circuits revealed positive improvement of the power-aware ERP algorithm in reducing total SoC test time

A Customized Reconfiguration Controller with Remote Direct ICAP Access for Dynamically Reconfigurable Platform

As FPGA dynamic partial reconfiguration getting into mainstream, design of reconfiguration controller becomes an active research. Most of the existing reconfiguration controllers support only the loading of partial bitstream into configuration memory without allowing user to access ICAP directly, which can provide user higher controllability over the reconfigurable device. This paper presents the architecture of a customized reconfiguration controller with remote direct ICAP access. Remote direct ICAP access allows user to configure or readback device internal registers, which offer user higher controllability over the reconfigurable device. Additionally, the proposed reconfiguration controller achieved at least 3.19 Gbps of reconfiguration throughput, which reduces the platform service downtime during dynamic partial reconfiguration. In order to reduce the latency and transmission overhead of remote functional update, partial bitstream is compressed with run-length encoding before transmission

An FPGA-based network system with service-uninterrupted remote functional update

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption

Accelerating Extreme Learning Machine on FPGA by Hardware Implementation of Given Rotation - QRD

Currently, Extreme Learning Machine (ELM) is one of the research trends in the machine learning field due to its remarkable performances in terms of complexity and computational speed. However, the big data era and the limitations of general-purpose processor cause the increasing of interest in hardware implementation of ELM in order to reduce the computational time. Hence, this work presents the hardware-software co-design of ELM to improve the overall performances. In the co-design paradigm, one of the important components of ELM, namely Given Rotation-QRD (GR-QRD) is developed as a hardware core. Field Programmable Gate Array (FPGA) is chosen as the platform for ELM implementation due to its reconfigurable capability and high parallelism. Moreover, the learning accuracy and computational time would be used to evaluate the performances of the proposed ELM design. Our experiment has shown that GR-QRD accelerator helps to reduce the computational time of ELM training by 41.75% while maintaining the same training accuracy in comparison to pure software of ELM

FPGA-Assisted Assertion-Based Verification Platform

In this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the firstin-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time

Configurable Version Management Hardware Transactional Memory for Multi-processor Platform

Programming on a shared memory multi-processor platforms in an efficient way is difficult as locked based synchronization limits the efficiency. Transactional memory (TM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, the performance of TM is application-specific. In general, the configuration of a TM is divided into version management and conflict management. Each scheme has its strengths and weaknesses depending on executing application. Previous TM implementations for embedded system were built on fixed version management configuration which results in significant performance loss when transaction behaviour changes. In this paper, we propose a hardware transactional memory (HTM) with interchangeable version management. Random requests at different contention levels are used to verify the performance of the proposed TM. The proposed architecture is targeted for embedded applications and is area-efficient compared to current implementations that apply cache coherence protocols

Quantification of tongue colour using machine learning in Kampo medicine

AbstractIntroductionThe evaluation of tongue colour has been an important approach to examine human health in Kampo medicine (traditional Japanese medicine) because the change in tongue colour may suggest physical or mental disorders. Several tongue colour quantification methods have been published to objectify clinical information among East Asian countries. However, reliable tongue colour analysis results among Japanese test persons are limited because of a lack of quantitative evaluation of tongue colour. We aimed to use advances in digital imaging processing to quantify and verify clinical data tongue colour diagnosis by characterising differences intongue features.MethodsThe DS01-B tongue colour information acquisition system was used to extract tongue images of 1080 Japanese test subjects. Evaluation of tongue colour, body and coating was performed by 10 experienced Kampo medicine physicians. The acquired images were classified into five tongue body colour categories and six tongue coating colour categories based on evaluations from 10 physicians with extensive Kampo medicine experience. K-means clustering algorithm was applied as a machine learning (the study of pattern recognition by computational learning) method to the acquired images to quantify tongue body and coating colour information.ResultsTongue body (n=550) and tongue coating (n=516) colour samples were classified and analysed. Clusters consisting of five tongue body colour categories and six tongue coating colour categories were experimentally described in the CIELAB colour space. Statistical differences were evident among the clinically primary tongue colours.ConclusionsClinically important tongue colour differences in Kampo medicine can be visualised by applying machine learning to tongue images taken under stable conditions. This has implications for developing globally unified, reliable tongue colour diagnostic criteria which could be used to explore the relevance between clinical status and tongue colour

Benzofuranyl Esters: Synthesis, Crystal Structure Determination, Antimicrobial and Antioxidant Activities

A series of five new 2‐(1‐benzofuran‐2‐yl)‐2‐oxoethyl 4-(un/substituted)benzoates 4(a–e), with the general formula of C8H5O(C=O)CH2O(C=O)C6H4X, X = H, Cl, CH3, OCH3 or NO2, was synthesized in high purity and good yield under mild conditions. The synthesized products 4(a–e) were characterized by FTIR, 1H-, 13C- and 1H-13C HMQC NMR spectroscopic analysis and their 3D structures were confirmed by single-crystal X-ray diffraction studies. These compounds were screened for their antimicrobial and antioxidant activities. The tested compounds showed antimicrobial ability in the order of 4b < 4a < 4c < 4d < 4e and the highest potency with minimum inhibition concentration (MIC) value of 125 μg/mL was observed for 4e. The results of antioxidant activities revealed the highest activity for compound 4e (32.62% ± 1.34%) in diphenyl-2-picrylhydrazyl (DPPH) radical scavenging, 4d (31.01% ± 4.35%) in ferric reducing antioxidant power (FRAP) assay and 4a (27.11% ± 1.06%) in metal chelating (MC) activity

Tachyon search speeds up retrieval of similar sequences by several orders of magnitude

Summary: The usage of current sequence search tools becomes increasingly slower as databases of protein sequences continue to grow exponentially. Tachyon, a new algorithm that identifies closely related protein sequences ~200 times faster than standard BLAST, circumvents this limitation with a reduced database and oligopeptide matching heuristic